1. Field of Art
The present invention generally relates to the field of electronic design automation, and more specifically, to electronic design automation using statistical static timing analysis.
2. Description of the Related Art
Electronic design automation (EDA) is used extensively in the design of integrated circuits. An electronic circuit under design is evaluated using models of devices and interconnections between the devices. A simulation using these models is then run to test the performance of the circuit.
Statistical static timing analysis (SSTA) is a methodology of electronic design automation for verifying whether the circuit under design meets desired timing criteria using statistical properties of the propagation delays. The probability distributions of the delays increase the complexity and the numbers of calculations run for SSTA.
From the above, there is a need for a system and process to provide an EDA model that reduces the numbers of calculations that are run for the statistical static timing analysis.